There is a continuous desire in the semiconductor industry to increase the density of components in a semiconductor device. A factor which greatly affects this desire is the micropattern techniques used in the formation of the components in the semiconductor device.
Furthermore, element formations stacked vertically on a substrate have been developed, increasing the thickness of the semiconductor layers. Because of this, device reliability is largely dependent upon the step coverage of a layer upon which another layer is stacked.
The spacing between individual layers is conventionally increased as the vertical stacking of components increases because of the improper alignment of the layers. Step coverage is degraded as the area for a contact window which allows for an electrical contact to a source or drain region between the elements is increased to, for instance, over 1.5 times the size of the source or drain region itself.
In addition, the degraded step coverage causes a decrease in the size of the contact windows formed, which in turn causes an increased contact resistance. This increased contact resistance lowers the current driving capacity of the semiconductor device.
Heretofore conventional research of stacking layers has left as inevitable the need for contact windows having a larger width-to-height (aspect) ratio as the vertical stacking of the layers increases. This invention provides a semiconductor device which allows for a reduced contact hole aspect ratio.
FIGS. 1A to 1C illustrate a-conventional process for manufacturing a semiconductor device whereby a contact window is formed which allows an electrical contact to be made to a transistor source or drain formed between the gates of a dynamic random access memory (DRAM) device.
Referring to FIG. 1A, a gate-insulating layer 12 is formed on a P-type silicon semiconductor substrate 11 of a silicon oxide or a silicon nitride by an oxidation method, a chemical vapor deposition (CVD) method or a physical vapor deposition (PVD) method. A polycrystalline silicon layer 13 is formed on the gate-insulating layer 12, and then a cap oxide layer 14 is formed on the polycrystalline silicon layer 13. The cap oxide layer 14 is formed of a silicon oxide via a high temperature oxidation (HTO) method.
A first photoresist pattern 15 is then formed on the cap oxide layer 14 by a conventional photolithographic process. The first photoresist pattern 15 protects a portion on which a gate 16 will be formed from being etched.
Referring to FIG. 1B, the portions of the cap oxide layer 14, the polycrystalline silicon layer 13, and the gate insulating layer 12 which are exposed by the first photoresist pattern 15 are successively removed by a dry or wet etching process, to expose the semiconductor substrate 11 and thereby form a gate 16. Thereafter, the first photoresist pattern 15 is removed.
Spacers (not shown) are formed on opposite sides of the gate 16. Then, using the spacers as a mask, a high density of N-type impurities are ion-implanted over the resultant structure to form the source and drain regions 17 having a lightly-doped drain (LDD) structure. An oxide layer 19 is then formed on the surface of the resultant structure via an HTO method. A second photoresist pattern 20 is then formed on the oxide layer 19 such that the oxide layer 19 between the gates 16 is exposed.
Referring to FIG. 1C, the portion of the oxide layer 19 which is exposed by the second photoresist pattern 20 is removed to form a contact window 21 between the gates 16. Then the second photoresist pattern 20 is removed.
A conductive layer 22 is then formed.
As described above, the conventional method for manufacturing a semiconductor device has the disadvantage of a decreased spacing between the gates 16. This is because the portion of the oxide layer 19 and the cap oxide layer 14 which was formed over the gates 16 is etched during the etching process for forming the contact window. This causes an etching of the exposed corner of the gate 16 prior to when forming the contact window to the semiconductor substrate.
Therefore, in order to prevent the corners of the gate 16 from being exposing prior to completion of the etching to the expose the semiconductor substrate, either a safe space must be securely maintained between the gates 16, or the thickness of the oxide layer 19 on the gate 16 must be increased.
However, according to the conventional method, the integration density of the semiconductor device is limited as the safe space is maintained between the gates 16. In addition, if the thickness of the oxide layer 19 on the gate 16 is increased, the aspect ratio of the contact window is increased and a subsequent layer, such as the metal lines deposited during the following metallization process, cannot completely fill up the contact window. Therefore, the conventional method has the disadvantage of deteriorated step coverage and reduced reliability of the semiconductor device.